This application claims the benefit of Korean patent application No. 96-62231, filed Dec. 6, 1996, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a thin film transistor of an active matrix liquid crystal display device and a method of manufacturing the same, and, more particularly, to a thin film transistor having a double gate layer and a method of manufacturing the same.
2. Discussion of the Related Art
In general, a thin film transistor (TFT) using amorphous silicon has an advantage in that a thin film semiconductor layer is formed on a glass substrate by a low-temperature process, and no leakage current is generated in the OFF state due to a wide energy band gap and a high resistance of the thin film itself. However, because the charge carrier mobility in the amorphous silicon of the thin film transistor is low, its current characteristic in the ON state is poor compared to a single-crystal or polycrystalline transistor. Moreover, the amorphous silicon thin film transistor does not employ a driving circuit on the same substrate.
A thin film transistor using polysilicon has higher charge carrier mobility and lower resistance than a thin film transistor using amorphous silicon, thus driving a large current in the ON state and forming a driving circuit with pixels on the same substrate. However, because the polysilicon thin film transistor has a narrow energy band gap and numerous Si dangling bonds, a large leakage current is generated around the drain region.
Therefore, a thin film transistor was developed having a LDD (lightly doped drain) region, or an offset region, to decrease the leakage current.
FIG. 1 is a sectional view of a conventional TFT. A buffer oxide layer 13 is formed on a transparent insulating substrate 11, and a semiconductor layer 15 is formed on a predetermined portion on the buffer oxide layer 13. A gate oxide layer 17 is formed on a predetermined portion on the semiconductor layer 15. A gate 19a is formed on a predetermined portion of the gate oxide layer 17.
The semiconductor layer 15 includes an active region 15a with no impurity doping, and an impurity region 15b where N type or P type impurities are highly doped to be used for the source and drain regions. The active region 15a consists of a channel region C1 where a channel is formed under the gate 19a, and an offset region O1 between the channel region C1 and an impurity region 15b. 
An aluminum gate 19a is formed overlapping the channel region C1 of the active region 15a. Anode oxide layers 21 and 27 are formed on the surface of the gate 19a. 
In the TFT described above, when a voltage is applied to the gate 19a, a channel is formed in the offset region O1 as well as in the channel region C1 due to an electric field, thereby turning the TFT on. When no voltage is applied to the gate 19a, no electric field is applied to the offset region O1, thereby preventing any leakage current.
FIGS. 2A-2D show the manufacturing process of the TFT. Referring to FIG. 2A, the buffer oxide layer 13 is formed on the transparent insulating substrate 11. The semiconductor layer 15 is formed on the buffer oxide layer 13 by depositing polysilicon. The semiconductor layer is patterned by a typical photolithography process to expose a predetermined region of the buffer oxide layer 13.
Referring to FIG. 2B, the gate oxide layer 17 is formed covering the buffer oxide layer 13 and the semiconductor layer 15. A gate metal layer 19 is formed by depositing an anode-oxidative metal such as aluminum, and the surface of the gate metal layer 19 is anodized to form a first anode oxide layer 21.
Referring to FIG. 2C, a photoresist pattern 23 is formed on a portion of the first anode-oxide layer 21. The first oxide layer 21 and the gate metal layer 19 are anisotropically etched using the photoresist pattern 23 as a mask. A part of the gate metal layer 19 that is not etched and removed becomes the gate 19a. The second anode oxide layer 25 is formed by anodizing the lateral sides of the gate 19a. The second anode-oxide layer 25 is anodized in a horizontal direction to define the offset region O1. In the anodizing process, large current flows to the gate 19a to speed up the anodizing of the gate 19a. As a result, the second anode oxide layer 25 is porous.
Referring to FIG. 2D, the gate oxide layer 17 is anisotropically etched using the photoresist layer 23 as a mask to expose a predetermined portion of the semiconductor layer 15 and the buffer oxide layer 13. The photoresist pattern 23 is then eliminated. Next, a third anode-oxide layer 27 is formed between the lateral side of the gate 19a and the second anode-oxide layer 25. Here, an electrolyte liquid makes contact with the lateral side of the gate 19a through the second porous anode-oxide layer 25 and therefore the third anode-oxide layer 27 is formed by anodizing the gate 19a. The second anode-oxide layer 25 is etched away, while the first and third anode oxide layers 21 and 27, which are denser than the second anode oxide layer 25, remain during the etching process. The second anode oxide layer 25 is removed entirely. Thus, the third anode-oxide layer 27 remains on the lateral side of the gate 19a. Thereafter, N type or P type impurities are highly doped into exposed portions of the semiconductor layer 15, using the first anode oxide layer 21 and the gate oxide layer 17 as a mask, thus forming source and drain regions 15b. Here, the remaining portion of the semiconductor layer 15 is the active region 15a. In this active region 15a, the portion overlapping the gate 19a becomes the channel region C1, while the portion between the impurity region 15b and the channel region C1 is the offset region O1.
As described above, in the conventional TFT the gate metal layer is patterned using the photoresist pattern 23 as a mask to form the gate 19a, the lateral sides of the gate 19a are anodized at a high rate without eliminating the photoresist pattern in order to form a second porous anode-oxide layer 25 in a horizontal direction, the photoresist pattern 23 is eliminated, and the portion between the lateral side of the gate and the second anode-oxide layer 23 is anodized to form the third anode-oxide layer. The third anode oxide layer 27 defines the offset region O1.
The conventional process for forming a TFT has certain drawbacks because it requires a complicated process to eliminate the lateral side of the gate 19a after the anodizing in the horizontal direction in order to define the offset region O1. Also, a hillock is generated due to the gate 19a consisting of Al.
Accordingly, the present invention is directed to a thin film transistor and method of manufacturing the same that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to provide a thin film transistor that does not have a hillock due to a gate.
Another object of the present invention is to provide a method for manufacturing a thin film transistor which can reduce the number of the processes by facilitating the definition of the offset region.
Additional features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a thin film transistor including an insulating substrate, a semiconductor layer formed on the insulating substrate and having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a portion of the active region of the semiconductor layer defining a channel region, and a second gate metal layer formed on the first gate metal layer.
In a second aspect of the present invention there is provided a method for manufacturing a thin film transistor, including the steps of forming a semiconductor layer on an insulating substrate, wherein the semiconductor layer has no impurity doping, depositing a gate insulating layer, a first gate metal layer and a second gate metal layer on the semiconductor layer, forming a photoresist pattern on a portion on the second gate metal layer, the photoresist pattern overlapping the portion of the semiconductor layer, and etching the first and second gate metal layers using the photoresist pattern as a mask to expose both sides of the first gate metal layer to form exposed portions of the first gate metal layer, wherein the second gate metal layer etches faster than the first gate metal layer.
In a third aspect of the present invention there is provided a method of manufacturing a thin film transistor, including the steps of forming a semiconductor layer on an insulating substrate, depositing a gate insulating layer, a first gate metal layer and a second gate metal layer on the semiconductor layer, forming a photoresist pattern on a portion of the second gate metal layer, the photoresist pattern overlapping a predetermined portion of the semiconductor layer, etching the first and second gate metal layers using the photoresist pattern as a mask to expose both sides of the first gate metal layer to form an exposed portion of the first gate metal layer, wherein the second gate metal layer etches faster than the first gate metal layer, anodizing the exposed portion of the first gate metal layer to form spacers, removing the photoresist pattern, forming impurity regions by doping impurities into exposed portions of the semiconductor layer, forming an insulating interlayer, removing a portion of the insulating interlayer to form contact holes exposing the impurity regions, forming source and drain electrodes making contact with the impurity regions through the contact holes, forming a first protective layer on the insulating interlayer and the source and drain electrodes, forming a light shielding layer covering a portion excluding a pixel region on the first protective layer, forming a second protective layer on the first insulating layer and light shielding layer, removing a portion of the first and second protective layers to form a contact hole exposing the drain electrode, and forming a pixel electrode on the second protective layer of the pixel region in contact with the drain electrode through the contact hole.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.